The present disclosure generally relates to memory devices and, more particularly, to caches implemented in one or more memory devices of a memory sub-system.
Generally, a computing system includes a processing sub-system and a memory sub-system, which may store data accessible by processing circuitry of the processing sub-system. For example, to perform an operation, the processing circuitry may execute corresponding instructions retrieved from a memory device of the memory sub-system. In some instances, data input to the operation may also be retrieved from the memory device. Additionally or alternatively, data output (e.g., resulting) from the operation may be stored in the memory device, for example, to enable subsequent retrieval. However, at least in some instances, operational efficiency of a computing system may be limited by its architecture, for example, which governs the sequence of operations performed in the computing system.